ISSCC 2017 / SESSION 6 / ULTRA - HIGH - SPEED WIRELINE / 6 . 1 6 . 1 A 56 Gb / s PAM - 4 / NRZ Transceiver in 40 nm CMOS

Figure 6.1.1(a) illustrates the TX structure, which consists of a 64:4 serializer, a 3-tap quarter-rate FFE, a poly-phase filter (PPF) generating quadrature clocks for the latches and selectors, and a combiner (output driver). The low-speed 64:4 serializer can be done in typical CMOS (digital) realization. The 4×14Gb/s inputs coming from it are fed into the quarter-rate FFE, which provides maximum boost of approximately 8dB at 14GHz (Nyquist frequency). Owing to the quarter-rate operation, most of the circuits are realized in CMOS (digital) format, saving significant power. A standalone 14GHz PLL incorporating a mixer-based PFD [1] to minimize jitter and spurs has been included, which is shared with the RX. The TX can be operated with the 14GHz clock either from the PLL or from outside. Sub-rate TXs are prone to output eye distortion, simply because of the imbalanced loading and routing. To overcome this issue, a duty cycle correction (DCC) unit is employed along the clock path. It provides a maximum tunable range of 40%~60%, well beyond any possible eye distortion. The DCC not only corrects the duty cycle, but also converts the CML clock to CMOS levels (i.e., rail-to-rail). The PAM-4 signal combiner is depicted in Fig. 6.1.1(b), where inductors are inserted between the differential pairs and the tail currents. The arrangement increases the high-frequency output impedance seen looking down to the current sources, maintaining relatively constant currents when the differential pairs are switching. As a result, the TX produces less ringing during transitions between levels, and the more eye opening can be achieved. Note that the pre-cursor and post-cursor paths employ a cascode structure, improving isolation between taps. The PAM-4 TX can deliver 28Gb/s NRZ data as well by shutting down half of the circuit (e.g., LSB path and Combiner 1).